State Level Workshop on Digital System Design using VHDL
This two day state level workshop on Digital System Design using VHDLon CPLD board was organized on 10 and 11 February 2012. In the workshop , we used ® Quartus®-II design software along with Altera U.P. Simulator.
We planned workshop with more emphasis on hands on training. With the help of specially edited lab manual we planned different lab exercises. This manual is organized into a series of specific programmable logic design tasks. Here we used CPLD Boards designed by Virtual Lab IIT, Bombay and interfacing board designed by our college. Dr M.B.Patil and Mr.Abhishek Kamath, Mrs M.S.Date (IIT, Mumbai) helped us in organizing workshop.
No of Participants
In the workshop, 20 faculty members and 48 M.Sc. students from different regions of Maharashtra like Nagpur, Amravati, Nashik, Ahmadnagar,Mumbai, Satara, Sangali And Pune had participated.
Practicals
- Half Adder , Full Adder
- 4:1 Multiplexer , 1:4 Demultiplexer
- BCD to Seven Segment code Conversion, Binary to Gray Converter,
- Gray to Binary Converter
- D, J-K , T Flip Flop
- Asynchronous Counter (Behavioral)
- Synchronous counter using T-FF( structural)
- EVEN-ODD Counter
- Universal Shift Register
- FSM: Sequence Detector
- One Digit Seven Segment counter
- Two Digit Seven Segment counter(Multiplexed Display)
- Stepper motor Sequence Generator (FSM)
- Two way Traffic Light Controller (FSM)
- Modulo-7 Counter using FSM Model
