One Day Workshop on Digital System Design using VHDL

13 March 2010

This workshop for M.Sc. students was organised  in the form of lecture series by following experts.

  • Dr. A.D.Shaligram Head, DOES, SPPU, Pune -PLD Architecture.
  • Dr. D.C.Gharpure DOES, SPPU, Pune-FSM
  • Mr. Kiran Kale , ASIC Engineer, Qlogic, Pune -Design tools used in Digital System Design.

No of participants – 60

 

Dr. A.D.Shaligram delivering a lecture.
Dr. A.D.Shaligram delivering a lecture.

 

Mr. S.S. Deshmukh , Vice Principal , Addressing students.
Mr. S.S. Deshmukh , Vice Principal , Addressing students.
L-R Mr. D.B. Gaikwad,Mr. Z.B. Pathan,Dr. A.D. Shaligram, Mr. S.S.Deshmukh
L-R Mr. D.B.Gaikwad,Mr. Z.B.Pathan,Dr. A.D. Shaligram, Mr. S.S.Deshmukh