One Day Workshop on Digital System Design using VHDL
13 March 2010
This workshop for M.Sc. students was organised in the form of lecture series by following experts.
- Dr. A.D.Shaligram Head, DOES, SPPU, Pune -PLD Architecture.
- Dr. D.C.Gharpure DOES, SPPU, Pune-FSM
- Mr. Kiran Kale , ASIC Engineer, Qlogic, Pune -Design tools used in Digital System Design.
No of participants – 60